synopsys has introduced what it describes as the industry’s first complete commercial IP solution for Compute Express Link (CXL) 4.0, targeting the growing demand for high-bandwidth memory connectivity in artificial intelligence and data center systems. The new IP is designed to help chip developers integrate CXL 4.0 connectivity into silicon while maintaining compatibility with earlier CXL generations.
CXL 4.0 doubles the link rate compared with CXL 3.x, increasing bandwidth from 64 GT/s to 128 GT/s through a PCIe 7.0-based physical layer. The specification retains the 256-byte FLIT format and adds support for up to four retimers per link as well as native x2 link widths. These capabilities are intended to help extend high-speed memory connectivity across rack-scale systems.
Synopsys’ unified IP architecture supports CXL 4.0, 3.x, 2.0 and 1.x, allowing a single solution to address multiple generations. The controller supports features including bundled ports and port-based routing. According to Synopsys, combining four x16 links can deliver more than 2 TB/s of bandwidth, while eight x16 links can exceed 4 TB/s.
The package also includes a PCIe 7.0-based SerDes PHY operating at 128 GT/s. Synopsys says the PHY has been hardened for advanced process nodes ranging from 5 nm to 2 nm. Its verification IP is designed to help manufacturers test compliance and interoperability before moving designs into production.
Security is another major component of the release. Synopsys’ Integrity and Data Encryption technology uses AES-GCM encryption and authentication for CXL.cache and CXL.mem traffic. The company says its implementation can provide encryption without adding cycle-level latency in skid mode. Support for TSP and TDISP protocols is also aimed at confidential computing environments.
The company is positioning CXL 4.0 as an important technology for addressing the AI memory bottleneck. As AI workloads and large language models require increasingly large amounts of memory, rack-scale memory pooling could allow computing systems to access shared memory capacity more efficiently.
Synopsys says its CXL 4.0 solution can help developers build next-generation AI infrastructure where high bandwidth, low latency, security and memory disaggregation are increasingly important. The release places CXL alongside technologies such as PCIe 7.0, UCIe, UALink and Ultra Ethernet within the company’s broader connectivity portfolio.
